It doubt that, because it requires 12.5 % more bits to be stored, with corresponding increase in cost.

ECC also doesn’t fully protect against Rowhammer, in particular if errors remain unreported: https://news.ycombinator.com/item?id=18508692

I think GP is talking about DDR5 "on-die ECC".

The percent increase depends on how many bits you're protecting in a group. It can be a lot smaller.

DDR5 does have "on chip ECC", but that doesn't protect as much as full ECC. Bit errors can be introduced after the bits leave the chip. It could happen on the ram chip pins, in the DIMM, the DIMM connector, the motherboard, the CPU pins, or in the CPU.

So it's not just the error reporting, it's protecting against errors on the whole pipeline, not just inside the chip.