The CPU itself has PCIe lanes, some of which are routed to the slots (PCI Express Graphics/"PEG lanes") and some of which are routed to the chipset. The chipset itself then provides multiplex capability to provide additional "chipset lanes" (but obviously having to share the bandwidth available over the trunk).
You could potentially put a 4.0 chipset on a 3.0 chip and it should nominally work, the chipset would provide 4.0 lanes to devices, but all the traffic would be multiplexed at 3.0 to go back to the chip so there wouldn't be a whole lot of point.
You could also put a 3.0 chipset on a 4.0 chip, which works fine and is even sensible for budget motherboards (this is how the AMD B550 chipset will work).
The things on the chipset tend to be slower devices that just need to be attached, not necessarily run fast. The chipset usually only gets 4 lanes total (so like, one NVMe drive saturates it) and hopping to the chipset adds latency which reduces IOPS on fast networking or Optane drives, reduces graphics performance for chipset-attached GPUs, etc.
You could potentially put a 4.0 chipset on a 3.0 chip and it should nominally work, the chipset would provide 4.0 lanes to devices, but all the traffic would be multiplexed at 3.0 to go back to the chip so there wouldn't be a whole lot of point.
You could also put a 3.0 chipset on a 4.0 chip, which works fine and is even sensible for budget motherboards (this is how the AMD B550 chipset will work).
The things on the chipset tend to be slower devices that just need to be attached, not necessarily run fast. The chipset usually only gets 4 lanes total (so like, one NVMe drive saturates it) and hopping to the chipset adds latency which reduces IOPS on fast networking or Optane drives, reduces graphics performance for chipset-attached GPUs, etc.