or an OpenPOWER system. The POWER9 chips are all 4.0 capable. So, basically everyone - on server and workstation - but Intel have a 4.0 capable chipset... well, isn't that amusing.
openPOWER systems, last I checked, cost something like $2800 for a bare kit with a single socket CPU and ATX size motherboard, that will be dramatically outperformed by a $109 motherboard and a $389 Ryzen. And significantly more for fully assembled ready to boot 2U / 4U size server chassis with motherboards.
It actually is just another type of SSD. It's just a NVMe drive.
It's a little confusing because Intel markets "Optane" as so many different things. "Optane" as marketed to the consumer is a combination of an Optane NVMe drive and motherboard-level support for disk caching. However, if you choose not to use the caching software, it just turns into a SSD.
The only catch is that most optane drives are pretty small. The consumer ones intended for cache are about 16GB. However, you can buy bigger ones up to about 120GB in M.2 format, and PCIe or U.2 based ones up to 1.5 TB aimed at the prosumer market.
AMD actually does really well with these because they have an extra x4 PCIe lanes (16+4 + 4 more for chipset) so you can run a graphics card at x16 speed and still have 4 more CPU-direct lanes for an Optane drive.
Then on servers you have Optane DIMMs which sorta-not-really replace RAM for massive in-memory servers.
Seems like it only works with Intel 7th gen and later.
Although there's a post on the LTT forums[0] exclaiming that Wendell managed to get it working. (although he also got Thunderbolt working before on AMD)
This is what happens when the marketing department gives the same name to two things which may be broadly in a general product category, but are technically very different. Have seen it with many categories of hardware.
That part isn't terrible, even though it is really unwieldy. The big problem is using "Optane Memory" as the branding for the kind that isn't a memory module.
The natural things to call them are "Optane drives" and "Optane memory". Don't criss-cross that!
Intel has basically been doing that for quite a while with the whole "Core i7", "Core i5", etc naming strategy. Where an i7 targeted at laptops might be substantially the same as an i3 targeted at desktops.
absolutely, for any meaningful comparison one has to track down what the code name for the CPU core is on various semiconductor enthusiast websites, and do ones' own research. There's like 10 different generations of core i3/i5/i7 now. I think the old i7 sitting behind me is an Ivy Bridge.
Yep. I have an Optane PCIe 3.0 4x add in card - 280GB drive - in an AMD TRX40 rig.
I don't imagine PCIe 4.0 will make much difference as a single drive can't make use of the extra bandwidth anyway - but I'm curious to see if there are improvements to the 3D XPoint memory. Kinda bummed I literally just bought mine.
try loading this page on mobile 3g/throttled lte. blank screen for a few seconds. text loads, some kind of pop up I scroll past and read about 2 paragraphs, when the text disappears, never to return again.
Honestly the most disheartening about that company was the half-baked NVIDIA shilling[1], that was called right away by the whole technical community[2].
I wouldn't get on my high horses about that, it's commonplace nowadays that former commercial media outlets have become "infomercial" businesses, essentially marketing agencies disguised as news/information outlets. The primary drive being that consumers of media don't bring enough revenue, whereas announcers and brands do, often shadily in this "new media" environment (undisclosed sponsorships, etc).
What you describe is, as I see it, just the rotten tip of Tom's iceberg.
Like you — and I know it may be biased — I tend to "identify" potential "red flags" just this way: rotten website (technically, cue Js) probably means shady business behind, in my book. Otherwise, why would you disingenuously break UX like that? Forbes comes to mind as an offender, and so many other formerly big names of the press. Just gone, in spirit and content, as of this century.
Worth noting afaik, Tom himself (the founder) sold and left a long time ago now (probably chilling on some tropical beach with his spouse
and kids? I wish him so).
Tom's was a good site...in the late 1990's. They were purchased somewhere in the 200's and turned to crap quickly.
Somehow they are owned by the same parent as Anandtech, which has gone downhill, is still readable. It's not total spam like Toms, even if I miss their in-depth Mac articles.
All these big sites were basically unreadable without lots of adblocking in my experience. I wouldn't attempt to look at anything until I set up a pi hole which was a huge game changer.
The CPU itself has PCIe lanes, some of which are routed to the slots (PCI Express Graphics/"PEG lanes") and some of which are routed to the chipset. The chipset itself then provides multiplex capability to provide additional "chipset lanes" (but obviously having to share the bandwidth available over the trunk).
You could potentially put a 4.0 chipset on a 3.0 chip and it should nominally work, the chipset would provide 4.0 lanes to devices, but all the traffic would be multiplexed at 3.0 to go back to the chip so there wouldn't be a whole lot of point.
You could also put a 3.0 chipset on a 4.0 chip, which works fine and is even sensible for budget motherboards (this is how the AMD B550 chipset will work).
The things on the chipset tend to be slower devices that just need to be attached, not necessarily run fast. The chipset usually only gets 4 lanes total (so like, one NVMe drive saturates it) and hopping to the chipset adds latency which reduces IOPS on fast networking or Optane drives, reduces graphics performance for chipset-attached GPUs, etc.
On low end desktop (1151 and friends), there are 16 PCI-E lanes directly from the CPU (typically used by the GPU), and the rest are connected to the PCH, which connects to the CPU with DMI. The main problem with updating the PCH alone here is that the link between the CPU and the PCH is only ~4GB/s, so PCI-E 4.0 speeds for the lanes extending from the PCH are rather pointless.
On HEDT and modern server, (2066 and friends), only about 8 of the PCI-E lanes come from the chipset, and the rest come directly from the CPU. The QPI and it's successor UPI is used to connect CPUs to each other, not to a chipset.
It's apparently UPI now[1], but they'll still need to do a lot of updating to the CPU and UPI to get the bandwidth of pci-e 4.0. Best info I can find[1] puts pci-e 4.0 x16 at around 64GB/s, and UPI at a max of 28GB/s on their best xeon cpus and fpgas. Having that kind of bottleneck at the chipset would make it nearly pointless since even pci-e 3.0 with a 16x link is 32GB/s.
Chipset doesn’t run at x16 bandwidth, it gets 4 lanes of bandwidth. At least for consumer platform, but I doubt server runs anything significant off chipset. QPI/UPI may run faster between sockets but I don’t think chipset is a full speed link by any means.
Nominally QPI/UPI but those protocols are not hugely distinct from PCIe in general. AFAIK it’s basically PCIe but encrypted, so that nobody else can replicate their chipsets (like used to happen in the old days with nForce/etc).
Also your numbers are off, easy rule of thumb is that one PCIe 3.0 lane is one GB/s of bandwidth per lane. So 3.0x16 is 16 GB/s of bandwidth.
So it just needs 8 GB/s of bandwidth to run at 4.0x4 speeds.
I have an Optane 900P PCIe 3.0 4x 280 GB and a Samsung 870 Evo Plus 1TB in the same system.
The Optane benches 3x faster on low queue depth 4k random reads. 4k writes are comparable. The Evo Plus beats the Optane by under 10% on deep queue 4k reads and writes and like 15-20% on sequential reads and writes.
They are mostly for Server / Database workload [1] and Facebook looked at reducing Memory usage with Optane[2].
Consumer workload see little to zero measurable benefits. Once you pass a certain Random Rd / Write speed, Seq Rd Write is still king, or likely not the source of bottlenecked.
What about developer workloads? Like reading hundreds of tiny files during compilation, writing thousands of tiny binary files after compilation, using disk-baked caches for IDE. I never found tests but for me it seems likely a scenario where Optane might help. Also things like starting a container or VM might be improved with Optane a little bit.
More RAM so your entire source tree is sitting in buffer cache is the way to go. The latency of hitting the SSD is way more than RAM, and for developer workloads (reading millions of tiny source code files to compile each one), latency is what matters.
You'll find often that these workloads are bottlenecked by network or CPU before they're slowed down by storage (especially the container and VM side). On compilation and IDE, is threaded I/O the most relevant way to think about those tasks? Phoronix has a threaded I/O benchmark that shows some significant increases in performance over other SSDs...
That is a good question and I often thought the difference would be so small and the main bottleneck to be CPU, now thinking a bit more may be it is a premature assumption.
One possible way to test this out is if you have enough RAM and just fit everything inside a RAM drive, basically removing all I/O speed concern and see if there are any significant improvement.
The Optane SSDs do quite well on any random access benchmarks; they are kind of specialised for it. For sequential access however, high-end prosumer SSDs like the Samsung 970 Pro beat the Optanes.
Random access latency is the bottleneck. You can feel the difference between NAND and Optane even if your sequential speeds are comparable to a hard drive, let alone the 2 gigabytes per second those drives can push.
After all, if you have to wait 100 microseconds per 4K read, a single thread can only utilize 40 megabytes per second.
Agreed. I am just saying that the Optanes are specifically tuned to be the fastest storage drives for random access -- and they deliver on that front. There are benchmarks out there, I can send you a link if you like.
As an experiment I put two of them mirrored as L2Arc in front of an 6 drive SATA600 SSD (Samsung 860 Pro) ZFS array (zfs equivalent of raid 0+1) for PostgreSql / graph databases. It seems to help a bit for random access hits, but not as much as I hoped. Fancy devices though
Scroll down and you'll see a graph comparing latency and IOPS for a 4kB 70/30 read/write workload on Alderstream (the codename for the 2nd gen Optane SSD), a NAND SSD (P4610) and the current Optane SSD (P4800X). It's just a snapshot for now, but I'm sure more is coming.
>Given that Intel doesn’t have any processors (aside from the Stratix 10 FPGAs) that support the PCIe 4.0 interface, the developers obviously don't have access to an Intel-driven test platform with the new interface
Beyond that, Stratix 10 is "shipping" in the sense that low-volume samples are being distributed to large partners, but it is practically impossible for anyone to buy a Stratix 10 in any formfactor other than dev kits.
And the non-$10,000 dev kits don't have PCIe 4.0.
The article is obviously about the lag Intel is experiencing with getting PCIe 4.0-capable products to the larger market.
You can get Zen 2 and POWER systems with PCIe 4.0 today, and it is highly likely that ARM-based motherboards supporting PCIe 4.0 will be available on the general market for actual purchase before Intel releases something.
One-offs, samples, test gear, and dev kits don't "count".
If they did, then PCIe 4.0 was first "available" in early 2016 because engineers got their first PLDA dev kits which allowed them to start prototyping their designs.
That sounds like a personal problem in need of a cold shower IYAM.
Be the change you seek by getting ISVs/OEMs/ODMs to launch an orgy of compatible hardware to simultaneous release peripherals to stick them with. Seems like an easy enough problem to solve, as long as everything is tested beforehand.
What's the business dynamic of Intel like? Would they be fine with customers using them with AMD CPUs or would they delay the product?