Nearly every chip in there is a WLCSP (wafer level chip scale package). Seems like the industry is trending toward no package is the package. Also, it will be interesting to see if there are any fan-out packages, like eWLB. Several IDMs have started integrating several ICs horizontally--usually things like audio codecs or USB transceivers. With multi-die fan out, you save a lot of PCB real estate. In small form-factor devices like the iWatch, packaging is a huge differentiator.

I pointed this trend out to a guy who was whining about the "good old days" of through hole components and how hard it was to use surface mount stuff. There are a lot of motivations to go with chip on board tech, mostly the chips can be cheaper as you have removed an entire chunk of steps and fallout out of the production process. Interestingly for me, the reason this is becoming more popular is that because feature sizes are so small, the silicon cost of these parts is dominated by the pin pads, not the logic. So making the pads big enough to put solder balls on them for COB assembly doesn't materially increase the cost of the die, and yet saves packaging, bondout, and post packaging testing.

Solder ball size is definitely a factor in modern packaging cost! Silicon area is really expensive. That's why places like where I work are developing fan-out wafer level CSP. It has all the benefits of water level processing cost, but extra area for solder balls is made of cheap mold, not expensive silicon.

These WLCSP parts are definitely not solderable at home though. But, with the rise of low cost PCB and assembly services, I'm not sure that matters as much as it used to. For example, one project I'm working on with a 384 ball BGA cost me twenty dollars to have placed and reflowed locally. And, new projects involve way fewer chips because of the scale of integration. As an analog engineer, it makes me sad, but I appreciate what I can make at home now!