It's a shame RMS made no reference to the current activity around RISC-V http://riscv.org/ a freely implementable instruction set architecture with BSD-licensed reference implementation.
At lowRISC http://lowrisc.org/ we aim to produce a fully open source SoC and produce it in volume. The aim is open source down to the HDL - that is the Verilog (or in this case Chisel) that describes the hardware. There is an extra step of place and routing the design for a specific process, but ultimately this relies on a process design kit for the process in question which comes with stringent NDAs. We are actually fortunate enough to be taking part as a mentoring organisation in Google Summer of Code in collaboration with a number of our friends in the wider open source software and hardware communities, so if you're a student and open hardware interests you there's an opportunity to get paid to contribute over the summer http://www.lowrisc.org/docs/gsoc-2015-ideas/
It was in Wired magazine, I'm sure that he needed to write with a certain level of concision. You might want to email him at rms at gnu dot org ... I've got to imagine he would support your efforts, and FSF has a hardware certification program, so couldn't hurt to try to open a line of communication
At lowRISC http://lowrisc.org/ we aim to produce a fully open source SoC and produce it in volume. The aim is open source down to the HDL - that is the Verilog (or in this case Chisel) that describes the hardware. There is an extra step of place and routing the design for a specific process, but ultimately this relies on a process design kit for the process in question which comes with stringent NDAs. We are actually fortunate enough to be taking part as a mentoring organisation in Google Summer of Code in collaboration with a number of our friends in the wider open source software and hardware communities, so if you're a student and open hardware interests you there's an opportunity to get paid to contribute over the summer http://www.lowrisc.org/docs/gsoc-2015-ideas/