Ugh. Well, I suppose it might be OK as long as it doesn't inherit anything about the DRAM hardware interface. Seriously, if you haven't seen how it works (test: are the timings tCAS, tRCD, tRP, tRAS familiar?) you are dramatically underestimating how ugly and restrictive the interface is. It's completely inappropriate for anything but DRAM and probably inappropriate for modern DRAM too. If not, it's probably because backwards compatibility with the interface has constricted DRAM design.

Speaking of which, I'd love to read a modern analysis of chip-to-chip serial vs parallel if anyone has one handy.