Disabling whole cores or lumps of cache to improve yields is one thing, but a lot of the features Intel is segmenting the market with are very tightly integrated with the rest of the chip. It would be extremely hard to detect and classify a defect as affecting HyperThreading or VT-x but leaving the core otherwise functional. It's a bit more plausible that defects in the high half of a vector SIMD unit could leave you with a SSE-capable but AVX-defective chip, but I suspect that in practice any broken functional units are treated as rendering the entire core inoperable.