That's just combinational logic, how do you implement clocked processes and latches?
In my (admittedly limited) experience with hardware design making correct pure combinational logic isn't generally too difficult, it's keeping track of the state and state transitions that's problematic.
I'm glad you asked. At the moment, only combinational circuits are possible, but I'm working to extend this to synchronous (clocked) circuits.
When you need feedback, there will be a combinator that will look something like this:
feedback : Vect n Bool -> (Vect i v -> Vect n v -> SSA op v (Vect n v, Vect o v)) -> Vect i v -> SSA op v (Vect o v)
This is all up in the air. I'm still working it through.
I'm very keen to end up with something that it nice to use, even at the expense of being difficult to implement.
I may be getting ahead of myself, but I'd like to have functions that do things like: take a combinational circuit and return a synchronous circuit where the logic is evenly separated (in terms of delay) over n clock cycles.
In my (admittedly limited) experience with hardware design making correct pure combinational logic isn't generally too difficult, it's keeping track of the state and state transitions that's problematic.