The nice thing with using an emulation system versus a raw FPGA board for learning is the same as debugging software with a source code debugger versus only having access to the disassembly.

In my experience, great hardware designers automagically write Verilog but think schematics.

A classic:

  always @(posedge clk) begin
    q1 <= d;
    q2 <= q1;
  end

And finally, most senior designers still get puzzled by one of my favorite quizzes:

what is the functional difference between those pieces of code, that both represent a flip-flop with async set/reset, one expressed in Verilog and one expressed in VHDL:

  always @(posedge clk or negedge rst or posedge set) begin
    if(!rst) q <= 0;
    else if(set) q <= 1;
      else q <= d;
  end

  process begin
  if(not rst) q <= 0;
    else if(set) q <= 1;
      else if(clk'posedge) q <= d;
  end process;

This could be fixed by using:

always @(posedge clk or rst or set)

I am guessing the thing that throws a verilog designer off the trail is that "always @(posedge clk or negedge rst)" is commonly used for asynchronous reset in ASICs (if you are using it in FPGA's except for the DCM's and as input to a clk-rst module.... stop), and this works just fine but if you want to do a d flip flop with an asynchronous SR condition, you can't use "negedge" on the rst signal.

However, synthesis will probably treat it asynchronously. Of course this is also bad because there will be a simulation/synthesis mismatch.

At any rate, the question is a bit ambiguous due to the unclear vhdl code.

Both code samples are the recommended way to generate an asynchronous set/reset flip-flop for an ASIC flow (minus my bad memory about details of the VHDL syntax).

For years, Design Compiler has forced ASIC designers to describe level sensitive pins (set or reset) as if they were edge triggered, which is correct in most cases, except the case you outlined.

So those two codes generate the exact same logic after synthesis, but you can have mismatches with simulation. And there is actually nothing you could do about it to fix the Verilog since you need your synthesis tool to understand your intent. The correction you propose is the correct one from a simulation viewpoint, but DC would reject it.

Luckily, the case where you assert both set and reset on a flop to then deassert reset are fairly rare...

I was on the IEEE standardization committee for VHDL synthesis: since then I know why [some] standards don't make sense.

http://users.ece.gatech.edu/~hamblen/book/bookse.htm

There is a third edition written around QuartusII - the current Altera software:

http://users.ece.gatech.edu/~hamblen/book/bookte.htm

I also found "The Designer's Guide to VHDL" (Ashenden) to be very useful for a deeper understanding of VHDL vs. the somewhat cookbook approach of the first book.

Ashenden has also written "The Student's Guide to VHDL" - no idea how good that is.

Some other links:

http://www.opencores.org/ Lots of VHDL and Verilog to examine

http://www.fpgaarcade.com/ Re-creating arcade machines

http://www.xess.com/ Nice development board (lots of good app. notes.) (I'm a satisfied customer)

Chandra Thimmannagari's CPU Design has a chapter on Verilog with many instructive short but nontrivial examples, in a novel compact format.

Out of several (expensive) books I do have, these are the ones that've been most helpful:

- Verilog HDL Synthesis by Bhasker - FPGA Prototyping by Verilog Examples by Pong P. Chu - Advanced FPGA Design by Kilts - The two "Learning By Example using Verilog" books by Richard Haskell (these are actually written specifically for use with the Digilent Nexys2 board I mentioned in an earlier post)

Many of the others are impractical, academic junk that waste your time with things like gate-level design, Karnaugh maps and the like that are handled by the synthesis tool nowadays. Unless you are writing a synthesis tool you don't need 75% of what's in most HDL textbooks.

Blank lines separate paragraphs. Leading hyphens don't do anything. And asking Paul Graham to rewrite a web forum in C is like sending Lance Armstrong to Paris on a unicycle.

Had it for about a year and a half, works like a charm. Xilinx also had a kit for $100 (maybe $150) that had a Spartan 2 and a CoolRunner II board, which was great in the early days. I think it's since been superseded by a Spartan 3 kit, but I don't know the pricing.

There is also http://www.xilinx.com/products/devkits/HW-SPAR3A-SK-UNI-G.ht... ($189)

Those Mac OSX users, what do you use for development? The Xilinx development software seems to work only in Windows and Linux.

The absolute best I've seen so far is the Nexys2 from Digilent. It's got the same Cypress FX2 high-speed USB chip and Spartan3E FPGA as the Xylo from fpga4fun.com/knjn.com but it costs $129 instead of $299, comes with full schematics, and gives you lots of switches, LEDs, and ports to work with too. Not to mention a good-sized external RAM (which I haven't played with yet).

I have an Analog Devices AD7760 eval board attached to my Nexys2's Hirose connector right now, and have had a lot of fun climbing the Verilog and JTAG learning curves with it.

I actually know some of the Digilent guys--their cofounder is an adjunct professor at my school and teaches using Digilent boards and curricula. He's probably one of the most busy and productive people I've ever met. As it happens, there's enough crossover between his work as an adjunct professor and his work at Digilent that it's more of a benefit to him as a cofounder than a distraction. It also puts him in a convenient position to be his own first customer, though he has hundreds of universities using his stuff too.