You might like my intro to ASIC/HDL course that I took as a junior at Purdue University. My team won an "AMD Design Award" for our VHDL implementation of a timing-attack-proof AES encryptor that sits on a PCIe bus. [0] Other, wanted, features were omitted (like decryption) for die space concerns. This animation was popular among my team. =)
One of the features that helped it win the award is that it used file IO for "language bridging". Most of the other projects were pure VHDL. Our project used Python to verify the VHDL and Python AES implementations against each other. Fairly simple (OK, VHDL file IO isn't great) in practice but very powerful in effect.
We also had an interactive demo where you would enter a block and key. The Python implementation would encrypt the block and print the output. We would also run the key and block through ModelSim running our VHDL implementation (making sure to go through the PCIe bridge). The output was displayed to the user, allowing them to "see with their own eyes" that the implementation was correct. It was a powerful demonstration. The other team that also won implemented a Java simulator for their 3D "GPU", at least as much as a GPU you can do in 2 mm x 2 mm with ~35 um feature size standard gates.
One of the features that helped it win the award is that it used file IO for "language bridging". Most of the other projects were pure VHDL. Our project used Python to verify the VHDL and Python AES implementations against each other. Fairly simple (OK, VHDL file IO isn't great) in practice but very powerful in effect.
We also had an interactive demo where you would enter a block and key. The Python implementation would encrypt the block and print the output. We would also run the key and block through ModelSim running our VHDL implementation (making sure to go through the PCIe bridge). The output was displayed to the user, allowing them to "see with their own eyes" that the implementation was correct. It was a powerful demonstration. The other team that also won implemented a Java simulator for their 3D "GPU", at least as much as a GPU you can do in 2 mm x 2 mm with ~35 um feature size standard gates.
0: https://github.com/jevinskie/aes-over-pcie