I tried to do a similar project in Spring 2007. I ended up with a mandate to teach a 10-week tutorial in Verilog to a small group of Intro-CS students. To start with I had them implement several basic projects like calculators and 7-segment scrollers.
For a finishing project I tried to have them implement the SAP-1 from Malvino & Brown's classic book, which they were already familiar with (http://www.amazon.com/dp/0028005945) -- It has a 8-bit word/bus, 3 registers, a 4-bit address space, and 4-bit single-operand instructions.
I had the idea that it should be pedagogically ideal, hopefully implemented as a single <30 line module, and couched in the motives of Alan Kay. Unfortunately I couldn't find a way to implement JMP in a single quasi-clock-cycle with a Von Neumann architecture. I had to rewrite it a dozen times, the first half getting it to synthesize, the latter getting it to place/route. Even once I got it running on a FPGA, the JMP never worked right.
I never thought to cheat by using a Harvard architecture, mostly because it would stop being anything like Malvino's SAP.
For a finishing project I tried to have them implement the SAP-1 from Malvino & Brown's classic book, which they were already familiar with (http://www.amazon.com/dp/0028005945) -- It has a 8-bit word/bus, 3 registers, a 4-bit address space, and 4-bit single-operand instructions.
I had the idea that it should be pedagogically ideal, hopefully implemented as a single <30 line module, and couched in the motives of Alan Kay. Unfortunately I couldn't find a way to implement JMP in a single quasi-clock-cycle with a Von Neumann architecture. I had to rewrite it a dozen times, the first half getting it to synthesize, the latter getting it to place/route. Even once I got it running on a FPGA, the JMP never worked right.
I never thought to cheat by using a Harvard architecture, mostly because it would stop being anything like Malvino's SAP.