The models themselves belong to the companies that make the software EDA tools for circuit simulation, i.e. Synopsys, Cadence, Siemens (ex Mentor).
While the models used in commercial EDA tools are based on those published by academic research, they may have various secret tweaks.
What belongs to the foundries, e.g. TSMC, Samsung, Intel, UMC, Global Foundries etc., or to the in-house semiconductor plants of certain companies, are the values of the model parameters, which are determined by fabricating and measuring a lot of test devices.
The foundries provide the model parameters to their customers included in the so-called Process Design Kits. For each semiconductor device fabrication process there is a PDK.
In order to design some custom integrated circuit, you need to obtain the PDK and install it in your simulation tools.
Unfortunately, the foundries with up-to-date fabrication processes keep secret their PDKs. Otherwise many people could attempt to design something like a CPU competitive with Intel, because unlike for fabrication, for design all you need is a computer and time.
Attempting to design a CPU using one of the obsolete PDKs that are available publicly, which are at the level used for CPUs like Pentium 4, more than 20 years ago, is futile, because the optimal design choices are very different for such ancient CMOS fabrication processes, in comparison with modern processes, so you would not learn more from that experience than when targeting an FPGA.
Isn't it that models themselves are public (like BSIM) but what you get in a PDK is a macromodel wrapping BSIM with another zillion of fudge factors, or at least binned by device size? That's what I understood by peeking into various PDK models.
Not every fab use BSIM models. Philips (now NXP) use PSP models for their own fabs and implement them as verilog-a code. This is a physics based model instead of fitted model like BSIM.
TSMC has their own C-library on top of BSIM models for FinFETs because BSIM isn't covering what they need. I don't know what will they use for GAA stuff.
While the models used in commercial EDA tools are based on those published by academic research, they may have various secret tweaks.
What belongs to the foundries, e.g. TSMC, Samsung, Intel, UMC, Global Foundries etc., or to the in-house semiconductor plants of certain companies, are the values of the model parameters, which are determined by fabricating and measuring a lot of test devices.
The foundries provide the model parameters to their customers included in the so-called Process Design Kits. For each semiconductor device fabrication process there is a PDK.
In order to design some custom integrated circuit, you need to obtain the PDK and install it in your simulation tools.
Unfortunately, the foundries with up-to-date fabrication processes keep secret their PDKs. Otherwise many people could attempt to design something like a CPU competitive with Intel, because unlike for fabrication, for design all you need is a computer and time.
Attempting to design a CPU using one of the obsolete PDKs that are available publicly, which are at the level used for CPUs like Pentium 4, more than 20 years ago, is futile, because the optimal design choices are very different for such ancient CMOS fabrication processes, in comparison with modern processes, so you would not learn more from that experience than when targeting an FPGA.