On your note about capacitor sizes — at my first EE job, my boss taught me about capacitance-voltage derating[0] for ceramic capacitors and it was quite the revelation. There is a significant inverse relationship between the two, which no one tells you about in college!
I'm now very careful to pick ceramic capacitors with enough headroom on their rated voltage as you lose a lot if you're close to the rated value. This curve is dependent on the different ceramic types as well (C0G, X7R, etc). Cheaper ceramics have a steeper rolloff.
For personal projects I am very careful to pick higher quality ceramics (X7R if I can) and use caps rated to 2-3x my operating voltage. Likely overkill, but I'm not optimizing for cost at volume.
It is not actually true that MLCC DC bias derating scales with voltage rating. The voltage rating itself actually has nothing to do with it. The correlation is with package size. (Package size and voltage rating are often loosely correlated (and were strongly correlated back in the day), which is where the misconception comes from.) The physical origin of the effect is electric field strength in the dielectric material; thicker dielectrics reduce the field strength, so you don't come as close to hitting the polarizability limit of the piezoelectric materials, at a given applied voltage. Voltage rating doesn't really show up in that analysis.
If you don't believe me, poke around a bit in SimSurfing or similar. You should also notice that most capacitors are actually binned by voltage rating these days: a 16V part and a 50V part might be identically specified, but one's curves just cut off at 16V. I don't know if that's strictly binning or just testing, but it's pretty clear they're the same parts under the hood.
> It is not actually true that MLCC DC bias derating scales with voltage rating. The voltage rating itself actually has nothing to do with it.
This statement used to be false (I used to design boards where I would bump the voltage rating to get better DC bias behavior), but it looks like the engineering behind these capacitors has changed "recently" (as in the last 10 years), and it is now mostly true.
Thank you (and the GP) for the correction! I'll admit this lesson came to me a decade ago and I am speaking to a rule of thumb I developed as a result. Time to update my knowledge banks.
The other thing worth mentioning is that there are multiple formulations, and they're not all equal. Just to pick on Murata, the last character of their part number is a reeling code (something so boring it's often omitted or wildcarded), and then the three characters before that represent the specific dielectric material in use. (Or something like that. It's a private use field and I'm reverse engineering it here.) For the examples above, that's "E01", "A01", or "A88". Each of those will behave differently in SimSurfing, but all parts with the same dielectric code will have the same DC bias behavior. (At least, they will if they have the same size and value, etc. When those change too, behavior still follows the usual trends.)
Parts with different codes can have vastly different behavior under DC bias. You'll find that one of them is the clear winner in most cases. Unfortunately, Murata knows this too, and that one is invariably more expensive in distribution.
But at least you can specify it!
Other vendors do this too, but it's easiest to see with Murata's setup and tools.
I'm now very careful to pick ceramic capacitors with enough headroom on their rated voltage as you lose a lot if you're close to the rated value. This curve is dependent on the different ceramic types as well (C0G, X7R, etc). Cheaper ceramics have a steeper rolloff.
For personal projects I am very careful to pick higher quality ceramics (X7R if I can) and use caps rated to 2-3x my operating voltage. Likely overkill, but I'm not optimizing for cost at volume.
[0] https://resources.altium.com/p/voltage-derating-ceramic-capa...