This is probably a stupid question but I don’t claim any knowledge here. Even though interconnect standards are moving to non-binary communication, doesn’t the signal eventually need to be converted back to a bitstream at its destination? Does this just push the bottleneck around, or do I just not understand the problem being solved? It’s almost certainly the latter and I’d love to understand more.
The important distinction is between on-silicon interconnects and off-silicon. On silicon, the interconnect density is much higher so it's feasible to get high bandwidth by having lots of "channels" (wide busses). This becomes less desirable off chip (on the PCB) for many reasons. Some of them are:
1) The interconnect density is much lower, and having such a large bus becomes physically large
2) The bus is larger and less precise, which makes maintaining skew between channels more and more challenging
3) The parasitic capacitance/inductance (i.e. energy storage) of the bus becomes larger as it gets physically larger, meaning each channel needs a relatively large driver circuit (which costs expensive silicon area) and dissipates more power to drive correctly, and even more power if the speed is increased.
Increasing the symbol complexity of each channel does more than just move the bottleneck around, because it allows fewer chip to chip interconnects to carry more data.
I don't work in this regime, but as a layman I'm not convinced using full QAM for on-board chip to chip interconnects makes sense. One major advantage you natively have over the RF case is you can be easily coherent (shared clock). Throwing this away to do carrier recovery introduces a lot of complexity and potentially reduces the available bandwidth. Assuming you transmit without a carrier, can you have "baseband" QAM without a separate I and a Q signal? If you transmit an I and Q signal separately, does that not just become the same thing as two PAM-32 signals?
There are a few drawbacks with transmitting QAM with two signals
- one needs 2 signals instead of one (2x total bandwidth)
- requires each channel bandwidth to extend to to DC, which had many other challenges
If one modulates the signal to shift it away from DC, the “negative/mirror” frequencies also shift, which means now bandwidth has doubled.
A QAM signal still has double the bandwidth of an equivalent PAM one but pays for it by encoding two PAM signals.
Of course, Discrete Multitone Modulation puts QAM to shame for non-flat channels as it can adapt near-perfectly to such. Not likely to happen for high speed interconnects in our lifetime. I suspect photonics will happen first.
A serializer/deserializer (serdes) is used to convert between high-speed serial I/O outside the chip (e.g. 100 Gbps) and lower-clocked parallel signals inside the chip (e.g. 64 bits at 1.5 GHz). Using serial protocols reduces the cost and thickness of cables while parallel wires are cheaper inside the chip.
Not a stupid question - you can think of the problem by analogy with RF engineering. You have very high performance digital logic and precise clocks on the chip that you can use to encode/decode (convolve/deconvolve) bits into waveform signals and time those signals before they leave the chip at minimal latency/power expense. Once the bits are off the chip, you have no such resource and are dealing with all kinds of impedance and noise issues, which is why there are separate circuits/logic dedicated to training and calibration of the encoding parameters of the signals sent over the wire in DRAM chips.
This more complex encoding scheme is just the next level in that process, indeed moving it closer to techniques used in RF engineering.
You’re right that the signals have to be converted back into bits at the destination. Basically, this solves the problem of pumping those bits at high speed across traces on a circuit board vs within a chip. The longer a signal has to go, the harder it is to maintain its integrity.
