I'm more curious if there is something that makes visualizing the Verilog easier... for instance, I've done some small projects where I used Digital [0] (which is so unfortunately named, but awesome) to put blocks of Verilog into the visual representation and then connect my blocks together (like ALU, block ram, registers etc) and run simulation. But the problem is taking all that out back to Verilog and then doing my synthesis with Yosys is a manual chore.
I am wondering if there is some sorta... IDE that is letting people inspect projects with lots in individual Verilog files quickly and show the structure visually (and manage test benches run Icarus and GTK wave etc). I haven't seen this outside of vendor-specific tools like Xylinx's Vivado and I'm wondering if I am just missing something or if that kinda of IDE doesn't exist in any open source tools just yet.
Edit- and yes I get that I'm probably just not used to the management of Verilog codebases and it's no different than software packages with lots of 'modules' and you just work on a module at a time and it isn't that crazy. But I find it odd that there aren't at least some more viz tools, considering functions of a CPU are so 'block' based... I'd love to be able to load up the RTL folder of one of the CPU projects and see how all these Verilog modules are connected to one another and to the top level. Size of the busses, number of instances, etc. As though it were a Logisim project.
I'd have also pointed you to Xilinx, more specifically their discontinued ISE product which we used for a university course. It did provide a schematic-style high level overview of how modules are wired together and also had a simulator which you could run from the IDE directly.
I reguarly use Vivado elaborated design view to browse RTL hierarchy. The schematic view, signal trace, etc is the best I've seen. You can also automate it with tcl, so I've used it to auto highlight clock domains in different colours, so you can see where crossings happen, etc.
Doesn't help with visualization, but there's a SystemVerilog/Verilog plugin for Jetbrains IDE (Clion etc) that is actually really helpful. Does renames, code completion, structural view, etc. like what you'd expect from a real IDE. I far preferred it to working in Vivado.
When I was using it, I used it with FuseSoC, and only dropped into Vivado when I needed to muss around with their "IP integrations, etc.
I am wondering if there is some sorta... IDE that is letting people inspect projects with lots in individual Verilog files quickly and show the structure visually (and manage test benches run Icarus and GTK wave etc). I haven't seen this outside of vendor-specific tools like Xylinx's Vivado and I'm wondering if I am just missing something or if that kinda of IDE doesn't exist in any open source tools just yet.
[0] https://github.com/hneemann/Digital
Edit- and yes I get that I'm probably just not used to the management of Verilog codebases and it's no different than software packages with lots of 'modules' and you just work on a module at a time and it isn't that crazy. But I find it odd that there aren't at least some more viz tools, considering functions of a CPU are so 'block' based... I'd love to be able to load up the RTL folder of one of the CPU projects and see how all these Verilog modules are connected to one another and to the top level. Size of the busses, number of instances, etc. As though it were a Logisim project.