I was privy to some discussion with people related to this line of research. In my layman understanding Chatterjee's contention was final placement of components in the accelerator chip was better done with some human aided intervention, after RL had generated a "mostly" complete layout.
Its not hard to imagine why he could be challenging the other paper - The RL program could possibly be generating placements based on optimization related to defined tasks (goals). The Nature paper shows a blurred out image of the same, where the components aren't symmetrical placed. However its understandable that interconnect lengths influence I/O which you want symmetrical from the similar components. That makes the placement more optimal for generalized tasks instead of specific ones.
Do we know if that is done? Maybe or maybe not. But it would be interesting to find out. Anyway this is something we'll better understand if Sat Chatterjee's preprint is released.
Its not hard to imagine why he could be challenging the other paper - The RL program could possibly be generating placements based on optimization related to defined tasks (goals). The Nature paper shows a blurred out image of the same, where the components aren't symmetrical placed. However its understandable that interconnect lengths influence I/O which you want symmetrical from the similar components. That makes the placement more optimal for generalized tasks instead of specific ones.
Do we know if that is done? Maybe or maybe not. But it would be interesting to find out. Anyway this is something we'll better understand if Sat Chatterjee's preprint is released.