The slides mention that the SGI RealityEngine had a programmable geometry engine. That geometry engine board alone held multiple (six or so?) Intel i860XP processors. Now I'm curious how much that whole thing must have cost new. The amount of hardware SGI threw at accelerated raster graphics was massive.
I have an SGI price sheet from July 1993. A 4xR4400/150Mhz, 64MB Onyx RealityEngine2 went for $199,999. Adding 64MB RAM cost another $11,000. The GE board had 12 i860 processors. The big rack-based system w/ 24 CPUs was $634,900.
And people complain about the prices of GPUs nowadays...
It might be an outdated note, but when I tried the same approach in 2015, I was limited not only by the GPU but also by the OpenGL version on the Linux I used. You had to enable some "extensions" in order to read back raw pixel data/buffers back from the GPU. Hope people have it easier these days.
Part of the reason for this is that the "raw" buffers you're reading back are not actually raw buffers. If you have raw access to the hardware (for example, using the graphics APIs on a game console) it turns out that they are typically using custom compressed representations and if you just want a buffer with pixels in it, the real buffer has to be decompressed, either in-place or into a temporary buffer. So when you are using that extension to read back raw data, what you're actually doing is kicking off a conversion operation on the GPU, then waiting and reading the contents of the buffer via DMA.
An excellent slide-set for the uninitiated - although if the first several slides assume a 3D graphics processing background. I especially like the perspective-switch from SIMD to NVIDIA/AMD-speak regarding threads and warps/wavefronts.
No, I don't think so. The TMS34010 is nothing like the 3D accelerators that these slides are about. The TI chip is a 2D graphics accelerator at heart, like a lot of the graphics hardware of the 80s. The SGI RealityEngine is noteworthy because it is an early hardware implementation of a 3D rasterization pipeline. The individual hardware boards of that system correspond almost exactly to the conceptual boxes you see in an introduction to the 3D rasterization pipeline.
PPL have to keep in mind that GPUs are all about extreme 3D performance, namely pushing the silicon really hard, then ASIC is probably the only reasonable way.
