> I have no clue about flags but why not just store the flags with the register? Each register would have 32+r bits where r is the number of flags.
That sort of design can be done, but that just pushes the problem around. Let's look at the original ARM 64 bit code:
adds x12, x6, x10
adcs x13, x7, x11
The second add with carry uses the global carry bit, it isn't passed as an argument to the adcs instruction. So if you store the carry bit with the x12 register, you would then need to specify x12 in the adcs instruction on the next line. So you need a new instruction format for adcs that can specify four registers.
You could change the semantics, where the add instructions use one register as the source and the destination, like on x86-64, but that's a whole 'nother discussion on why that is and isn't done on various architectures.
That sort of design can be done, but that just pushes the problem around. Let's look at the original ARM 64 bit code:
The second add with carry uses the global carry bit, it isn't passed as an argument to the adcs instruction. So if you store the carry bit with the x12 register, you would then need to specify x12 in the adcs instruction on the next line. So you need a new instruction format for adcs that can specify four registers.You could change the semantics, where the add instructions use one register as the source and the destination, like on x86-64, but that's a whole 'nother discussion on why that is and isn't done on various architectures.