The naming of the process does not provide any direct information about the performance of the transistors.
The process name is supposed to mean that if the size name is twice smaller than in the same area you can pack 4 times more transistors.
So the 3LPE process is supposed to have a transistor density about one hundred times larger than the 32-nm processes that were used for Intel Sandy Bridge or AMD Bulldozer, or about 3600 times larger than the 180-nm process used for the first Pentium 4.
The performance of individual transistors is usually worse for smaller transistors (except for the energy consumed by switching a single transistor, which is obviously smaller), but that is compensated by using more complex circuits, with more transistors, but not much more, so there is still a gain in density by going to smaller transistors.
The process name is supposed to mean that if the size name is twice smaller than in the same area you can pack 4 times more transistors.
So the 3LPE process is supposed to have a transistor density about one hundred times larger than the 32-nm processes that were used for Intel Sandy Bridge or AMD Bulldozer, or about 3600 times larger than the 180-nm process used for the first Pentium 4.
The performance of individual transistors is usually worse for smaller transistors (except for the energy consumed by switching a single transistor, which is obviously smaller), but that is compensated by using more complex circuits, with more transistors, but not much more, so there is still a gain in density by going to smaller transistors.