I've met Dennis years ago at a vintage computer festival. He later visited our hackerspace to present his MyCPU project - a computer he built from ground up, including the CPU, graphics card, operating system and everything else. He's an amazing guy and his visit is one of the best memories I have of that place. Our hackerspace is gone now and I'm so happy he's still doing projects like this.
This reminds me of Dave Taylor's idea for "pinky processors". These were similarly minimal, relying on conditional branches to do much of the work. Taylor thought massive numbers of these clocked at high frequencies would deliver more computation than complex high-IPC processors. He was wrong, as the failures of the Pentium 4 and AMD's Bulldozer would later demonstrate, but at least he was ahead of his time.
Unlike Taylor's ideas, this MyNOR actually exists in the real world, which is all the more impressive considering how impractical it is.
the ideas like MyNOR dovetail nicely with the couple posts/discussions here recently about rebooting/bootstrapping the civilization. One can imagine several situations where we'd have to go back to basics - wars, catastrophes and/or colonies on other planets or even generational ship, etc. I mean in the situation without modern technology available, we know how to make simple crystal diode and with a bit of small effort transistor and that would let us build very simple computer along the lines of the MyNOR ...
One can also imagine it in the other direction - how a traveler from the year 3000 would try to build a quantum-quark-multidimensional-time-accelerated MyNOR of the year 3000 using the year 2020 technology - i mean we probably already have some pieces allowing to build a crude version of it.
What sort of simulator is required to go from “running” to ordering a prototype board 26 days later?
I had assumed physical breadboards and wires and chips were always necessary to prototype...
2019-11-02 The first version of the MyNOR simulator is running. The circuit works!
2019-11-17 I have finished the work on the microcode. I added support for MyNOR to my cross-assembler myca.
2019-11-28 PCB layout completed. A friend told me about JLCPCB, so I ordered the prototype board there.
Nope. I design electronics professionally and I rarely do breadboard prototypes (and almost never using a solderless breadboard). This is because I can be reasonably confident about the behaviour of most circuits with perhaps a little bit of simulation using a SPICE model for some analogue parts. For complex digital logic (which is very rare to design using seperate ICs these days, you would use an FPGA) there is a multitude of simulation systems you can use as well to test your design (including some of the design tools for FPGAs).
PCBs can be made cheaply and on short notices these days (I can get 5-off a 4-layer PCB for $200 in 4 days, and that extends both cheaper if I can wait longer and shorter if I want to pay more), and solderless breadboards are atrocious for almost anything I'd want to prototype (the parasitic capacitances, inductances, and resistances are all really bad. sensitive analog circuits, high-speed digital, and power electronics all suffer badly from those).
When I was in university, we used Logisim[0] for our intro to digital logic class. I think you could probably simulate such a computer in this tool if you wanted something intuitive. Otherwise you can prepare your design in a high level logic language like Verilog and test it using Verilator [1]. Naturally there is always a risk when going from running in a simulator to the real PCB.
The simulation tool for Altera FPGA:s was pretty powerful when I used it a few years back. You'd basically drag and drop "packages" like the 74xx components, connect them and you could run the circuit with timing profiles and all. The purpose is of course not to actually then build it out of discrete logic but to synthesize it to a FPGA bit stream, but once you have the tool setup (it required something like 200 gigs if disc space and was extremely picky about drivers) I can see it being an option for this sort of thing.
Professionals generally have enough confidence to go straight to PCB. Solderless breadboards have enough capacitance that they aren't suitable for high-speed digital logic anyway.
Solderless breadboards are the equivalent of exploratory programming. If you know what you want to make you might as well go for a PCB (you can simulate the logic quite nicely these days).
True, the parasitic capacitance of those boards is horrible. Personally I wouldn't even try to go over 5 or so, but that leaves room for plenty of interesting and educational projects.
Makes it pretty hard to hide an Internet backdoor in it.
Seriously, I wonder if this is a way to make a secure and open computer, by implementing the deepest level of security functionality in slow but visibly trust-able hardware.
> While the move to smaller transistors has been a boon for performance it has dramatically increased the cost to fabricate chips using those smaller transistors. This forces the vast majority of chip design companies to trust a third party -- often overseas -- to fabricate their design. To guard against shipping chips with errors (intentional or otherwise) chip design companies rely on post-fabrication testing. Unfortunately, this type of testing leaves the door open to malicious modifications since attackers can craft attack triggers requiring a sequence of unlikely events, which will never be encountered by even the most diligent tester. In this paper, we show how a fabrication-time attacker can leverage analog circuits to create a hardware attack that is small (i.e., requires as little as one gate) and stealthy (i.e., requires an unlikely trigger sequence before effecting a chip's functionality). In the open spaces of an already placed and routed design, we construct a circuit that uses capacitors to siphon charge from nearby wires as they transition between digital values. When the capacitors fully charge, they deploy an attack that forces a victim flip-flop to a desired value. We weaponize this attack into a remotely-controllable privilege escalation by attaching the capacitor to a wire controllable and by selecting a victim flip-flop that holds the privilege bit for our processor. We implement this attack in an OR1200 processor and fabricate a chip. Experimental results show that our attacks work, show that our attacks elude activation by a diverse set of benchmarks, and suggest that our attacks evade known defenses.
> "There are two ways of constructing a software design: One way is to make it so simple that there are obviously no deficiencies, and the other way is to make it so complicated that there are no obvious deficiencies. The first method is far more difficult."
I've been thinking about this too. I don't think the hardware needs to be this weak/slow. It just needs to be analyzable. Modern silicon chips can only be inspected with electron microscopes, and even then, they have multiple layers, so it's a non-starter. You could probably spend multiple lifetimes studying a modern chip.
On the other hand, if you take a chip like the good old ARM1, it's a 32-bit chip with no cache and about 25K transistors. If you fabricated it with an older process, with a single layer, it might be possible to inspect it with a regular microscope, and you could use basic computer vision to compare the layout against a reference implementation that you have an HD picture of. It's a relatively weak chip, but you may be able to clock it at 50 or 100 MHz. It's fast enough to run basic UI apps and networked services. It's 32-bit so you could address a few gigabytes of RAM (well, maybe not with an ARM1 design, but with a comparable 32-bit RISC-V, say).
This is pretty cool, since there is no word size you can chose to compute numbers of any size you want when you write the program. It's pretty fitting for a calculator application.
This is amazing! I had a question about this passage however:
>" MyNOR is a single board computer that does not have a CPU. Instead, the CPU consists of discrete logic gates from the 74HC series ..."
Isn't that still a CPU just not a integrated chip or microprocessor? Isn't a board with discrete logic gates basically how mainframes and minicomputers such as PDP-11 etc were built before the advent of the "microprocessor"?
From the very first few lines of the description I was wondering how this could be possible. The problem isn't the NOR gate - that's definitely enough for all computation - but how to drive it. Looking at the schematic, it is only wired to bit 0 in the data bus, which is 8 bits. So how do you perform ALU ops on all the other bits? There is no shift data path. How can an 8-bit CPU use a 1-bit ALU with no barreling/bit multiplexing?
It took me a while to find the answer in the description of the add instruction:
It uses a lookup table to perform bit rotates. Unfortunately, this kind of breaks the entire idea of a one-NOR ALU data path. Now you have a table-driven 8-bit rotate ALU op (which is the same amount of table space needed for a 4-bit add!), and at that point you might as well ditch the NOR gate and implement everything else in microcode tables too. You can use lookup tables to implement any logic function, of course.
IOW I bet you could just modify the microcode of this thing to make it much faster by replacing the core of the ADD with another table.
Conversely, you can also just implement the NOR operation (or anything else) as control flow in the microcode sequencer, if you have any way to test bits instead, giving you a "zero-gate" ALU (ed: yeah, there is a conditional jump microinstruction).
So while this is definitely a very cool project and interesting design, I do find the claim of one-NOR purity questionable. It cheats. In a fun way, but this isn't a 1-NOR ALU CPU, it's a highly microcoded table-driven CPU that uses a two-transistor NOR gate as a gimmicky ALU component :-)
For implementing a faster ADD with the existing design, tables, and ditching the NOR, the tricky bit is mixing the inputs. One simple optimization would be to have a table that implements "rotate and add one" and one that implements "rotate". Then you can just test bit 0 of one operand, use that to select a table (via control flow) to apply to the second operand, then rotate the first operand, and repeat (2 table lookups). No NOR ops necessary. You could test two bits and cut it down to 3 table lookups per 2 bits added, or 5 table lookups per 4 bits added by just adding more tablespace. The issue here is you still need the flop+NOR to mix inputs bit by bit (even if just as control flow), but since addresses are split into halves, you could also have a table that converts one operand into the right table address MSB to index a 4-bit addition with rotate, for each nybbke. That gives you 8-bit addition in 4 table lookups, 256+256+4096 bytes of tables, and no conditional jumps, flip-flop, or NOR necessary. I bet there are other better ways of doing this too.
It's obvious a lot if work went into the project and I salute the creator.
This is a computing device made out of 74 series chips. I wonder when I'll see a computing device on HN made out of discrete transistors, capacitors, etc
This was made from a netlist that was reverse engineered from microscope images of the 6502 die, and I think uses a roughly similar die layout. It uses discrete transistors and a handful of transistor array ICs (because you need an exposed "body" pin in order to make a functional pass gate).
This is very impressive, especially the add ons like the calculator and Lcd, show how much work can be done with 2600 instructions per second when things are highly optimized.
I think the idea is that you use registers and apply the NOR gate multiple times. In this sense the NOR gate is universal, while an OR gate nor a XOR gate are neither universal.
Any expression or series of gates of only ORs has the non-decreasing property, changing an input from 0 to 1 can never change the result from 1 to 0. So you can't implement any gate that needs that using ORs.
Similarly, any collection of XOR gates is simply a summation mod 2.
That’s just moving the composition between hardware and software - the equivalence still applies. I can build any logic (software) function out of a function that evaluates NOR.
Not really. It's completely trivial, if extremely slow (which the article acknowledges) to emulate an ALU in software, with access to a single, universal hardware gate. Why don't they just say "we put a NOR gate on a chip, then added all this other stuff (RAM, boot EEPROM, etc.) to make it function as a computer." That would, at least, be a non-misleading statement of the claim.
What's amazing about these projects is that "home computers" could have been around a few years earlier, before single-chip CPUs were available in quantity and at reasonable cost.
I assume it's the same reason many tube amplifiers expose their tubes... they want to highlight their differentiator and for you to see them for exactly what they are.
The project doesn’t say that there isn’t a counter, but just that the ALU is a single NOR gate. Obviously, that’s not enough for an ALU, but through repeated operations (such as with microcode), it can be enough.
Why one would do this? Probably for fun; There’s no practical application of this that I can see.
I used to work for a company that produced Flash Memory developed on NAND gates. Later, they attempted a product line of FPGAs... you keep calling this a CPU, but it seems similar to a FPGA. How is this different than a FPGA (if at all)?