> Same instruction (JALR) used for both calls, returns and register-indirect branches (requires extra decode for branch prediction)
JALR for call and return used the same opcode but are two different instructions, there is no need for "extra logic" for the decode or for branch prediction.
The lack of "register + shifted" could easily be circumvented by adding an extension for "complex arithmetic instructions".
And macro op fusion is a common solution that already exists in modern CPUs to increase the number of stages in the pipeline.
> Multiply and divide are part of the same extension
An extension can easily be partially supported in hardware (e.g. multiplication) and leave the other instructions emulated in software (e.g. divisions)
> No atomic instructions in the base ISA. Multi-core microcontrollers are increasingly common
But some microcontrollers do not need atomics. And if you are designing a microcontroller that does, just include the atomic extension.
Many of the criticisms made here are incorrect and are due more to a misunderstanding of RISC-V than to RISC-V design flaws
JALR for call and return used the same opcode but are two different instructions, there is no need for "extra logic" for the decode or for branch prediction.
The lack of "register + shifted" could easily be circumvented by adding an extension for "complex arithmetic instructions".
And macro op fusion is a common solution that already exists in modern CPUs to increase the number of stages in the pipeline.
> Multiply and divide are part of the same extension
An extension can easily be partially supported in hardware (e.g. multiplication) and leave the other instructions emulated in software (e.g. divisions)
> No atomic instructions in the base ISA. Multi-core microcontrollers are increasingly common
But some microcontrollers do not need atomics. And if you are designing a microcontroller that does, just include the atomic extension.
Many of the criticisms made here are incorrect and are due more to a misunderstanding of RISC-V than to RISC-V design flaws