Vop2 are the "2-source / 1-destination" instruction format. You can see from the table that GCN 1.0 and GCN 1.2 don't even line up at all.
It wouldn't be hard to compile GCN 1.0 into GCN 1.2 instructions, but it wouldn't be binary-compatible, just assembly-language compatible (like 8080 -> 8086).
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Some other facts:
* RDNA is Wave32 native. Wave64 compatibility is available though, so that should mostly work for backwards compatibility (aside from DPP, which you do point out may not exist in PS4)
* S_WAITCNT ("wait for memory" instruction) has grossly changed in RDNA. In GCN, waiting for VM_CNT(0) will wait on loads and stores. But VM_CNT(0) only waits for loads on RDNA.
You need to change every S_WAITCNT VM_CNT(0) (GCN) into S_WAITCNT VM_CNT(0), followed by a new S_WAITCNT_VSCNT 0 instruction (wait for 0 outstanding loads, THEN wait for 0 outstanding stores).
This isn't "binary compatible", but if you just inserted one instruction on every GCN S_WAITCNT, you'd get the proper behavior in RDNA.
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I'm seeing GCN -> RDNA as a "mostly easy compile" between the assembly languages. But it doesn't seem binary compatible to me. I wouldn't be surprised if there were one or two issues that popped up however.
I'd be surprised if this fact was true.
GCN 1.0 and GCN 1.2 aren't even binary compatible. Opcode 0x1 is "ReadLane" in GCN 1.0, but is "Add F32" in GCN 1.2.
https://github.com/CLRX/CLRX-mirror/wiki/GcnInstrsVop2
Vop2 are the "2-source / 1-destination" instruction format. You can see from the table that GCN 1.0 and GCN 1.2 don't even line up at all.
It wouldn't be hard to compile GCN 1.0 into GCN 1.2 instructions, but it wouldn't be binary-compatible, just assembly-language compatible (like 8080 -> 8086).
--------
Some other facts:
* RDNA is Wave32 native. Wave64 compatibility is available though, so that should mostly work for backwards compatibility (aside from DPP, which you do point out may not exist in PS4)
* S_WAITCNT ("wait for memory" instruction) has grossly changed in RDNA. In GCN, waiting for VM_CNT(0) will wait on loads and stores. But VM_CNT(0) only waits for loads on RDNA.
You need to change every S_WAITCNT VM_CNT(0) (GCN) into S_WAITCNT VM_CNT(0), followed by a new S_WAITCNT_VSCNT 0 instruction (wait for 0 outstanding loads, THEN wait for 0 outstanding stores).
This isn't "binary compatible", but if you just inserted one instruction on every GCN S_WAITCNT, you'd get the proper behavior in RDNA.
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I'm seeing GCN -> RDNA as a "mostly easy compile" between the assembly languages. But it doesn't seem binary compatible to me. I wouldn't be surprised if there were one or two issues that popped up however.