Depends a lot on your CPU's architecture as well as workloads, how far ahead it prefetches vs how often it's stalled on large memory reads. So it's hard to know. e.g. Zen+ (Ryzen 2000) was seeing 10% in some gaming workloads going from DDR4-2400 to DDR4-3600, but it's much less drastic on Intel CPUs or even Zen 2 (Ryzen 3000) because the memory controller is smarter so the slower RAM is less of a detriment. And then if you go above 3600mhz (or 3800mhz if overclocked) on zen 2 you start getting negative returns for a bit because the CPU memory controller can no longer run at the same clock as the memory and that induces overhead. But maybe a 4800mhz if it can be stable easier gets far enough ahead of that penalty that the improvement goes positive again. Or maybe Zen 4/DDR5-lake just works with memory entirely differently and the performance gains are massive or neglible.
The short of it is it's very hard to make predictions here.
The reason Zen1 (and 2) speed up a lot from ram speed increases is because the memory controller speed is tied to ram speed. So when you bump up the ram speed you also bump the memory controller speed, which reduces ram latency and inter-cpu communication latency.
There is no telling what the memory controller -> ram ratio will be with ddr5, the memory controller has speed limits, so you aren't going to get free speed just because the dr5 starts at 4800, because the zen memory controller can't run that fast anyway.
Zen 2 IMC can do DDR4-5000, but it's rather pointless, because it requires un-coupled mode with IFCLK != UCLK (since IFCLK cannot be pushed to more than ~1.9 GHz, and even that is not stable on many CPUs), which adds so much latency that you _need_ DDR4-5000+ to approach the performance of DDR4-3800 with IFCLK = UCLK.
>even Zen 2 (Ryzen 3000) because the memory controller is smarter so the slower RAM is less of a detriment
Source? I'm not of zen 2 having a "smarter" memory controller that improves performance. AFAIK the only improvements that they did implement (that could be construed as relating to the memory subsystem) was larger caches and a better branch predictor.
The short of it is it's very hard to make predictions here.