I have a (likely silly) question for anyone well versed in low level CPU stuff. §20.7 says there's a stack engine that optimizes manipulation of the stack pointer. Does this only apply to the dedicated hardware register (ie %rsp) or to other registers as well?
(Potentially related, assuming it's of benefit are modern compilers smart enough to repurpose %rsp (is this even allowed?) if I use a block of memory as a stack inside a hot loop?)
Take this with 2 cents since I'm not versed explicitly in Zen architecture, but it's likely only the SP. Usage patterns are fairly easy to deduce at compile time and are optimized, i.e. loop tiling, thus I think it's fair to assume the optimizations are leveraged against this. For example, if you can predict the loop pattern you can repurpose the SP.
(Potentially related, assuming it's of benefit are modern compilers smart enough to repurpose %rsp (is this even allowed?) if I use a block of memory as a stack inside a hot loop?)