1. As nodes were getting smaller, and metal layers thinner, the power had to migrate lower, and lower in the backend, where they compete for space with signal traces, and add to cross talk problem
2. Smaller, and smaller power rails had bigger, and bigger leakage.
3. As more, and more exotic device geometries were appearing, the more limitations on how power delivered to them were appearing.
4. Voltages were getting lower, and lower, and copper losses, and demands on DC-DC regulators higher.
Buried rails attack 1) by simplifying cell design, and taking cross-talk out of the picture as such. Signal simply doesn't compete with power at all now; 2) By allowing buried rails be made as big as needed, and on top of that, they can be buried in High-K; 3) By making just any geometry in Z axis possible without power influencing its design; 4) By increasing conductor sizes, as said above, and allowing for placing regulators on the other side of the wafer using TSVs.
1. As nodes were getting smaller, and metal layers thinner, the power had to migrate lower, and lower in the backend, where they compete for space with signal traces, and add to cross talk problem
2. Smaller, and smaller power rails had bigger, and bigger leakage.
3. As more, and more exotic device geometries were appearing, the more limitations on how power delivered to them were appearing.
4. Voltages were getting lower, and lower, and copper losses, and demands on DC-DC regulators higher.
Buried rails attack 1) by simplifying cell design, and taking cross-talk out of the picture as such. Signal simply doesn't compete with power at all now; 2) By allowing buried rails be made as big as needed, and on top of that, they can be buried in High-K; 3) By making just any geometry in Z axis possible without power influencing its design; 4) By increasing conductor sizes, as said above, and allowing for placing regulators on the other side of the wafer using TSVs.