Following the link to SO, from there the link to RWT, and from there the link to the previous page in the review, it mentions "The new port 6 on Haswell is a scalar integer port. It only accesses the GPRs and the integer bypass network." which makes me think that the "not enough space on the die" might not refer to the space for the Port 7 Store AGU itself, but to the resources it uses. The address modes with the index register need to read two registers, while allowing only "base+offset" means it only has to read one register. I don't know how expensive an extra read connection to the integer bypass network would be, but I have read that read ports for the register file are expensive, to the point where having two identical copies of the register file (written in parallel) to reduce the number of read ports per copy can be considered a valid optimization. So the "not enough space" might also be for the register file (AFAIK register files use a lot of area, which is why RISC-V has a variant with half the number of registers for some embedded use cases) or its connections.
Following the link to SO, from there the link to RWT, and from there the link to the previous page in the review, it mentions "The new port 6 on Haswell is a scalar integer port. It only accesses the GPRs and the integer bypass network." which makes me think that the "not enough space on the die" might not refer to the space for the Port 7 Store AGU itself, but to the resources it uses. The address modes with the index register need to read two registers, while allowing only "base+offset" means it only has to read one register. I don't know how expensive an extra read connection to the integer bypass network would be, but I have read that read ports for the register file are expensive, to the point where having two identical copies of the register file (written in parallel) to reduce the number of read ports per copy can be considered a valid optimization. So the "not enough space" might also be for the register file (AFAIK register files use a lot of area, which is why RISC-V has a variant with half the number of registers for some embedded use cases) or its connections.