14 nm in actual distance is only ~50 silicon atoms (~1.4 angstroms) wide. 14 nm process finFETs have a fin width of ~8 nm and in general 14 nm process transistors have a gate length of ~20 nm.
> Such as what’s the resistance of a wire 1 atom wide?
Quite high; you also get a lot of leakage since electrons are basically scattering elastically all the time. You can't use copper for a wire like this, you need special low-scattering conductors.
Unless I am missing something the general transister density for 14nm is vastly worse than that.
If an A9 has 2 Billion transistors on a 96 mm^2 chip. That's ~45,000 transistor in a row ~= 10 mm = 10000000 nm or 35,000,000 atoms. Or 1 transistor per ~777x777 atoms except that’s across multiple layers so hand wave ~1,000 atoms.
Not least because a transistors are not nice neat npn regions. They have multiple gates, all different gate sizes, all number of inputs, outputs and regions.
Intel manages to cram 20 million SRAM cells per mm^2 with 14nm; each cell has 6 transistors. That's three times higher than their reported density of 45 million per mm^2. More to the point, the transistor density really isn't that important. For one thing there are three regions and four terminals in every transistor, so it doesn't make much sense to collapse all that to a single atom.
It also doesn't make much sense because that wouldn't offer much benefit: those regions and the space between transistors are pretty minor issues compared to the increased switching efficiency from shrinking the gate, which is the truly important part and the limiting feature. Electricity moves at a significant fraction of c, which moves 30 millimeters every clock @10 GHz. Enough to completely cross a CPU multiple times, which it should never need to do.
> Such as what’s the resistance of a wire 1 atom wide?
Quite high; you also get a lot of leakage since electrons are basically scattering elastically all the time. You can't use copper for a wire like this, you need special low-scattering conductors.