If you used your microscope slide as a mask to do photolithography on silicon, you'd use an optical reducer, right? So the feature size on the silicon could be ~5x smaller?
I believe current tech uses 4x reduction from masks down to actual chips. This works well with sizes needed for quartz lens systems, etc. Older processes used 1x reduction (either direct contact, or very tiny offset). This is cheaper and easier because you don't need any quartz lenses, which are needed instead of standard glass for their UV transmission ability.
Interesting. I've got a 180nm mask from a previous job. It's obviously a larger scale than the finished chip. Could be 4x. I think it is from TSCM, circa 2003, for mixed signal CMOS.
