> The article didn't say if the increase applied equally to both electron mobility and hole mobility.
Electron mobility is not high in silicon, but it has never been a "blocker" before. In fact, the utilisation of strained silicon has gone down from 40nm in later nodes.
Silicon however has truly terrible hole mobility, and the wider industry has just started to realise that they have lost many years to fruitless pursuit of high electron mobility, when the real blocker has always been a pFET.
It was very prudent of TSMC to quietly continue pFET RnD, despite industry's fixation of HEMTs and 3-5 devices.
p.s. 5N is a COAG process from what they have just said.
> The amount of Ge and thus strain has increased every node.
Not really from what I know. The compressive strained channel was dropped out for some FinFET designs, and I think tensile strained too in some because it was exploding litho layer count. Can you tell your source?
Compare the amount of money spent on truly moonshot material science like making 3-5 logic, and the amount of money spent on continuous improvement of pfet performance for mainstream applications.
From device cross sections and working at both IDMs and suppliers. And reading and visiting IEDM for a decade. You can keepmup with ost on semiwiki: but really, just work under the assumption that people in the field are not stupid and can do math.
Tensile strains has no litho impact, and counting layers in use was a job I had.
Who spent on 3-5? It got press coverage, but never was part of much logic research. It was a focus for power, laser, and led work.
Tsmc, Intel, applied, asm, and others spent vastly more on r&d than any government or academic work, and it isn't published.
I'll give you that. I haven't been involved with device and process development since around 2009, when I lost hope getting into process engineering.
So, were strained channels used with FinFETs on anything mainstream? I heard the news of number of foundries dropping straining at around the time of first finfets.
Electron mobility is not high in silicon, but it has never been a "blocker" before. In fact, the utilisation of strained silicon has gone down from 40nm in later nodes.
Silicon however has truly terrible hole mobility, and the wider industry has just started to realise that they have lost many years to fruitless pursuit of high electron mobility, when the real blocker has always been a pFET.
It was very prudent of TSMC to quietly continue pFET RnD, despite industry's fixation of HEMTs and 3-5 devices.
p.s. 5N is a COAG process from what they have just said.