AMD's strategy of using multiple Zen 2 dies (7nm) tied together by a 14nm I/O die (since I/O doesn't scale down quite as well) is a really interesting strategy to improve yields using smaller dies (rather than making huge, low yield chips like the competition) & reduce mask/production cost. One 7nm Zen 2 mask can be used to produce CPU cores for a multitude of SKUs, optimizing for different markets using (cheaply customized) I/O interconnects made on 14nm.
This allows for AMD to keep much less silicon on hand for stocking the myriad of SKUs, as the only bottleneck for ramping up production of a SKU is producing those I/O interconnects on 14nm, which is a well understood process.
I think you replied to the wrong comment, but this also allows AMD to manufacture the IO die with glofo, which saves cost not only because 14nm capacity is much higher, but also since AMD's agreement with glofo requires them to pay a fee for every wafer they manufacture with another fab.
This allows for AMD to keep much less silicon on hand for stocking the myriad of SKUs, as the only bottleneck for ramping up production of a SKU is producing those I/O interconnects on 14nm, which is a well understood process.