When you've got a generation of top talent tinkering with an ISA that doesn't suck like x86, you're going to see adoption in actual industry.
RISC V is not much more than a slightly tweaked MIPS, the previous "preferred academic architecture", and we all know what happened to that... much to the chagrin of those who thought MIPS would be "the future of computing".
My prediction is that it will probably replace MIPS where it's currently used (very low-end tablets and phones, and a lot of home routers), but won't really displace ARM or x86. A "pure RISC" like MIPS and now RISC V just doesn't have the "CISCness" that makes successful CPUs beyond the theoretical.
Look at the results for the Loongson. It has at least twice as much cache as the others and 4-way OoO, yet after normalising for clock frequency and process power, it manages to be dead last in efficiency on 3 out of 4 of the benchmarks.
I've been following trends in the industry since the 90s. The "RISC dream" is still very much a dream. Trying to get an overly simple and restrictive ISA to perform well is sheer folly. Things that the RISC proponents thought would matter (decode complexity, number of architectural registers, addressing mode complexity) actually didn't, and what they thought wouldn't matter (memory bandwidth/latency, clock speed, instruction density), did. A denser, more intel-ligent (pun fully intended) ISA is what x86 and ARM is moving toward, while the MIPS/RISC advocates are going backwards.
I don't see why a RISC-V core can't be built to run as fast or as efficiently as an x86 on the high end. With the C extension for compressed (16-bit) instructions, the dynamic and static code size is very close to x86 and usually better than armv8 over a slew of practical benchmarks.
This is a processor comparison. The Loongson is the only 90nm chip here. No wonder it has no chance against 32nm and 40nm chips. The 60nm A8 also performs horribly.
It's more CISCy than MIPS/RISC-V. It does a reasonably good job of having complex instructions that closely match real world patterns, as opposed to some of the crufty bits of x86 that are complex... and useless.
The "crufty bits of x86" did "match real world patterns" when they were introduced (and neither ARM nor MIPS even existed)... and some still have surprising uses: https://news.ycombinator.com/item?id=8477254
But in general, these more complex instructions are where most of the microarchitectural optimisation happens. The BCD instructions mentioned in the above link were originally implemented in microcode and took dozens of cycles; for example, AAD took 60 cycles on an 8086, but only ~4 on a Skylake (and can be scheduled in parallel with the uops of other instructions) --- despite the little use it has today. A look at instruction timing tables[1] shows that the common idea of little-used instructions receiving no optimisation or even becoming much slower with each new processor generation is mostly false (there are exceptions, like the ill-fated P4.)
RISC V is not much more than a slightly tweaked MIPS, the previous "preferred academic architecture", and we all know what happened to that... much to the chagrin of those who thought MIPS would be "the future of computing".
My prediction is that it will probably replace MIPS where it's currently used (very low-end tablets and phones, and a lot of home routers), but won't really displace ARM or x86. A "pure RISC" like MIPS and now RISC V just doesn't have the "CISCness" that makes successful CPUs beyond the theoretical.
https://www.extremetech.com/extreme/188396-the-final-isa-sho...
Look at the results for the Loongson. It has at least twice as much cache as the others and 4-way OoO, yet after normalising for clock frequency and process power, it manages to be dead last in efficiency on 3 out of 4 of the benchmarks.
I've been following trends in the industry since the 90s. The "RISC dream" is still very much a dream. Trying to get an overly simple and restrictive ISA to perform well is sheer folly. Things that the RISC proponents thought would matter (decode complexity, number of architectural registers, addressing mode complexity) actually didn't, and what they thought wouldn't matter (memory bandwidth/latency, clock speed, instruction density), did. A denser, more intel-ligent (pun fully intended) ISA is what x86 and ARM is moving toward, while the MIPS/RISC advocates are going backwards.