This is a very old (I think > 15 years ago) competition, the results say nothing about the situation today, both language have changed a lot.

It was a PR stunt by the Synopsys guys who a that time wanted to kill VHDL. The VHDL guys had to work with slow & broken VHDL simulators. The the problem was devised by verilog enthusiasts. All VHDL engineers who showed up (in much smaller numbers than verilog engineers) felt like they they didn't have a fair chance.

TL;DR:

1. Guy worked for synopsis

2. Unlike competition synopsis didn't have a vhdl product

This poat was heavily cirticized when it was published.

For the language subset needed for this test, the languages are EQUAL (different syntax, same structure and outcome).

Also, the guy who run the competition (and his employer) have for years tried to kill vhdl (for personal and $$$ reasons).