It pains me though that you haven't experienced a 'real' logic analyzer (and that is in quotes because they are all real but originally they were different).
So originally, the way the logic analyzer worked was that you had a 'clock' module and 'data' lines. The clock module fed a clock signal into analyzer and you told it so sample the data lines on the rising, falling, or both clock edges. It was done this way because all digital logic works on the clock edges. You could also 'oversample' where you ran the system clock through a clock doubler or quadrupler or octupler and used that as your clock source. That would let you look at a signal multiple times. Most of the doubler circuit patents[1] have expired so using them/building them is fine.
Given that setup you could analyze your logic using the clock the logic was using and everything just worked. To translate back into 'real' time you either had to measure the logic's clock or annotate the samples with a free running clock built into the analyzer.
What you have built, and a lot of people have experienced on things like the Rigol scope and elsewhere, is more like a 'digital oscilloscope' where you digitally sample the inputs at a given frequency. This is fine for doing serial bus decoding (especially if you can sample at 16x the bus frequency) but it doesn't help on logic analysis if your tracking down timing issues. Because the signal may have changed state at any time between the sampling interval you can't check setup or hold times accurately.
There's been various discussions around here, and often the Raspberry Pi comes up. The Raspberry Pi is a great board and everything, but this "Logic Analyzer" use case is a great example of where a Microcontroller should be used rather than a general-purpose computer.
The STM32F746G looks like a far "weaker" processor. 216MHz, only 320KB of RAM... the "Computer" specs look utterly awful compared to the Raspberry Pi Zero. Indeed, the Rasp. Pi Zero costs only $10 while the NUCLEO-F746ZG costs $25.
However, what is important in this application is not necessarily raw speed... but speed coupled with CONSISTENCY, as per diagram "B". The particular feat is this:
> It can reliably read GPIO inputs every 3th or 4th clock cycle on many devices
You will never get this level of consistency from a Raspberry Pi. Indeed, it looks like it was only achieved through careful programming + use of the DMA channels + careful work thinking about who is using RAM and who isn't (to not over-burden the on-board memory controller).
That's the world of microcontrollers in a nutshell. Its about the focus on delivering consistent performance rather than high-performance.
Perhaps not on Linux. You don't need to run Linux on SBCs. At least not exclusively.
Some SBCs also contain additional non-ARM processors on the SoC, which could be used for the purpose of data acquisition.
For example Orange Pi has H3, which contains OpenRISC core that can run at 300MHz or so from code located in internal SRAM. I haven't tried yet, but I guess you can get pretty consistent results with this approach too: Main cores running on Linux processing the data, OpenRISC accessing GPIO and reading the data in a tight loop, throwing them to main memory into some ring buffer, or into part of the SRAM.
Well, I was talking about the Raspberry Pi Zero specifically, which doesn't have those RISC cores.
One particularly cool Single-board Computer (SBC) is the Beaglebone Blue. The Beaglebone Blue came with "PRUs" (Programmable Realtime Units), which seem similar to the OpenRISC core you are talking about. Such "embedded microcontrollers" exist because the main computer. There are also a hell of a lot more GPIO pins, ADCs, Servo-channels, Motor-controls, and other such stuff to assist the robotic designers.
No need for "Realtime" Linux either, if you're focusing on the PRU / alternative cores to do the heavy-lifting. So I didn't want to discriminate against SBCs as much as I wanted to highlight the importance of low-latency and consistent reads off of pins. Two things that the Raspberry Pi is pretty dismal at doing.
Its fine, ycombinator is a web-technology, software-focused message board. YCombinator cares about web-technologies, keeping up with Linux Kernel patches, and the like. And that's good and important.
However, embedded and microcontroller features are often ignored, despite embedded topics popping up around here pretty often. So I felt it necessary to bring up the compare/contrast.
With regard to the PRUs, I don't think the BB Blue has anything the BB, BB Black, and BB Green don't. They all have the PRUs. It's a function of the AM335x Cortex-A8 SoC.
At this point, you need a time machine to get a BB Blue, anyway.
You'd get more consistency for sure, but nothing that approaches the 75MHz (13 nanoseconds!!) needed to capture data from the GPIO pins.
From my understanding of the Raspberry Pi, the GPIO pins simply weren't designed for that level of speed. Which is fine, the Raspberry Pi was designed for other stuff. Its all about tradeoffs.
Maybe not capture, but you can write to the pins at least that quickly. I've seen projects that use the gpio of a raspberry pi to drive an FM transmitter at 100MHz.
Ah, my bad. I was actually thinking afterwards about how they could be doing the frequency shifts and what kind of sampling speed they would need for accurate, small frequency shift adjustments.
And that's pretty much it- Lattice includes "Reveal" a logic analyzer which can run on the FPGA in their tools. It's intended to debug designs, but there is nothing stopping you from capturing data from pins. Pretty sure it would capture signals up to ~200 MHz.
When your entire chip is programmable-logic, you don't have much room for RAM. The MachXo3LF-6900 has a grand total of 240 kBITs, or 30kBytes of storage.
In contrast, the STM32F746G will get you 320kBYTES of storage, 10x the capacity.
At 75MHz and 1-bit per cycle, that's still only 35ms of storage. Furthermore, it'd be a lot easier to program a Microcontroller to compress the data as its reading it, rather than use the FPGA.
The Microcontroller will still get you the Ethernet and USB connections too.
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I think this is a job for a microcontroller, not an FPGA. FPGAs are nice and flexible of course, but Microcontrollers offer you far more performance if you're going to use the specific features.
The STM32F746G has GPIO -> DMA directly to its RAM, while the CPU can compress 1/2 of the signal and send it out while the GPIO pins are simultaneously working. That's... pretty good. I have doubts that a cheap FPGA can accomplish all that at the same speed.
I believe the FPGA is often being used for converting fewer high speed inputs, to a greater number of lower speed outputs for the GPIO of the FX3, I think that's called SerDes (please correct me if I'm using that phrase incorrectly).
Speed isn't the only consideration here. 5x the speed needs 5x the RAM to store it in. But FPGAs will NEVER have as much RAM as a dedicated microcontroller.
Again, you're looking at ~320kBytes on the $25 STM32 microcontroller board, against ~30kBytes on the $25 FPGA board. With 1/10th the RAM, the FPGA will store far less useful data.
The typical Oscilloscope is like 100MHz. Getting a cheap 75MHz logic analyzer is perfectly acceptable. Storing and processing all that data (ie: outputting it to an Ethernet port) start to become the main issues once the speed issue is solved.
In my experience, those small FPGAs run out of room rather quickly too. Throw down something as simple as a Wallace tree multiplier and suddenly half your LUTs are eaten up.
The "embedded" solution is: buy embedded on-board SRAM when you need it, and if necessary, buy an embedded on-board SRAM memory controller if you need it. Building your own memory-controller out of an FPGA sounds like hell to layout.
Anyway, if we're talking about cheap stuff, DDR3L isn't the technology of note. This is about simpler SDRAM-level stuff, maybe a few MB at a time is sufficient.
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Furthermore: How many LUTs will your memory controller take up?
According to this, Lattice's DDR3L 16-bit memory controller is 2500 LUTs. The $25 FPGA only has 6300-LUTs, so you've already used up 40% of the chip on just memory-interfacing!
Yeah, you can accomplish a lot with a $600 FPGA with a Million-bajillion-LUTs and embedded cores. But at the $25 price point, FPGAs often run out of room. You don't have many LUTs to work with.
Dollar-for-dollar, a microcontroller will outperform an FPGA in most tasks. That's just the facts. ASIC-implemented memory-controllers and ASIC-implemented large banks of internal SRAM just work better for computer-like tasks.
FPGAs should be used for custom logic that isn't typically handled by a microcontroller / microprocessor. Not memory-controllers and ALUs that already exist in an easily packaged form. There's a reason why high-level FPGAs have embedded ARM cores and embedded memory-controllers in them (alas: such technology is likely out of the reach of cheap $25 FPGAs)
Includes 45K LUT FPGA with 250KB on-die RAM, DDR3, controller license and PCIe.. Actually this is so cheap I wonder if they are about to discontinue it.
Anyway, I otherwise think the capture the data with the DMA trick is cool. There are a bunch of projects which do the reverse: generate video with SPI output with tricks to make jitter free sync signals.
Only 1/3rd for the DDR3 controller? That's a great result, given the remainder of a logic analyzer is.. well let's just say there is not much to it, even with protocol decoding.
The point here is: you can get the DDR3 IP block, put it into your FPGA, and your timing will still work just fine. Which is of course kind of a big deal here. I can't put close to the level of logic in a DDR3 interface in a microcontroller and still have it hit the correct timing; all of that pretty much falls apart at the mention of "pipelining" or "vectored interrupt controller". Try doing protocol decoding on the same microcontroller that does the sampling.
Erm, you just buy a microcontroller that supports DDR3 out of the box if you care about large amounts of RAM. There are literally thousands of microcontrollers out there, with a configuration for every single possible task imaginable.
In contrast, you "contact the sales office" of an IP-block of Verilog and read through a ton of FPGA documentation.
I mean, if you really want to just "buy one chip" and do everything with it, be my guest. But honestly, its sometimes easier to just go to a different page in Digikey and buy what you need, instead of trying to build everything you need every time.
I don't think you quite realize what kind of microcontrollers would even come with a DDR3 interface. But if you want to waste away a > 500 MHz chip with sampling GPIO and DMAing that to memory (good luck hitting anything close to what an FPGA could do here, that kind of chip tends to come with multiple levels of caching, pinmuxing, ...) you must have a large BoM and power budget.
Point. I think most of the chips I was thinking about are simpler SDRAM controllers.
Nonetheless, I still think that you're grossly underestimating the needs of the FPGA / Logic Analyzer. The product communicates to the PC over USB for instance, performs RAM-level compression and seems to handle some logic-analyzing tasks as well (considering it natively supports I2C, UART, and the like).
EDIT: I think I see where you're coming from now. The next steps then would be licensing issues then. Like whether or not a company could effectively sell the IP-block of the memory-controller and distribute it over the internet (as what has happened in this project).
Sure, an FPGA does the job faster, but how popular are the FPGA boards compared to something like STM32 Nucleo? What we are trying to achieve is make a software logic analyzer that will work on top of the hardware that everyone has for prototyping anyway. 8 boards is just the beginning...
Oh yeah, we looked into the open-source ones. The main problems there were irregular sampling and software that will make you sweat before you get your first reliable measurement. So we wanted to create something that will be extremely easy to use and will reliably work out-of-the-box.
The Cypress FX2 boards from eBay/Aliexpress seem popular for streaming logic analysers too. I bought a variant which uses the FX2 chip along with an FPGA.
It pains me though that you haven't experienced a 'real' logic analyzer (and that is in quotes because they are all real but originally they were different).
So originally, the way the logic analyzer worked was that you had a 'clock' module and 'data' lines. The clock module fed a clock signal into analyzer and you told it so sample the data lines on the rising, falling, or both clock edges. It was done this way because all digital logic works on the clock edges. You could also 'oversample' where you ran the system clock through a clock doubler or quadrupler or octupler and used that as your clock source. That would let you look at a signal multiple times. Most of the doubler circuit patents[1] have expired so using them/building them is fine.
Given that setup you could analyze your logic using the clock the logic was using and everything just worked. To translate back into 'real' time you either had to measure the logic's clock or annotate the samples with a free running clock built into the analyzer.
What you have built, and a lot of people have experienced on things like the Rigol scope and elsewhere, is more like a 'digital oscilloscope' where you digitally sample the inputs at a given frequency. This is fine for doing serial bus decoding (especially if you can sample at 16x the bus frequency) but it doesn't help on logic analysis if your tracking down timing issues. Because the signal may have changed state at any time between the sampling interval you can't check setup or hold times accurately.
[1] https://www.google.com/patents/US5111066 as an example