For logic gates there is a "setup" and "hold" time (logic level prior to gate flip, then hold that level) for an operation to be successfully performed and transmitted to the next stage. It should be in the chip's datasheet (if you wanted a precise and specific number). If you don't care about logic transmission and just want "flip" then look at the rise/fall time.
It depends on PVT. Process, Voltage, and Temperature. When chips are being synthesized all this is characterized for each logic cell like and gates, flip flops, etc. They are in .lib files that is sent into the synthesis tools. If you can get one of those files it will tell you all the numbers.
20ns corresponds to 50 MHz. Recent CPUs run at over 1 GHz, so 20ns is completely off. And the clock frequency includes many gates on its critical path.
