Yeah, you can do that. Shifts the risk to the expensive, black boxes made in pro-espionage countries. ;) Plus, your volume is really, really low. When Im home, I'll give you link to a defunct fab in Europe that did theirs that way. Might be worth copying for some sectors.
Alright, this is just one of those topics that it's hard to get prior Google results out of that were good. All papers have same terms in them. (sighs) I did find something to illustrate the problem, though.
This describes micromilling semiconductors with focused, ion beams. Now, you said not FIB lithography. I can't be sure this is what you're talking about but it's pretty direct. Regardless, all the schemes work similarly in that you work on one part at a time across a chip or wafer. In this one, you can see the precision work is so time consuming that it can take 8 hours for first, metal layer in a chip with quite a few of them. Another part says days. Whereas, even old uses of masks with steppers were cranking out three wafers per minute. See the difference? That's why the direct technologies, even multiple beams, are usually used for just the photomask (most fabs) or for prototypes (eASIC).
I did find that fab I was telling you about that used tech like this:
It was doing it on nodes that are ancient by today's standards. Yet, you could do quite a bit with them. The lead time was only four weeks for quite a few chips at a reasonable price. Better capabilities can be had at less price today. I keep saying target 0.35 micron initially as it's inexpensive with many fabs available and last cheap one with visual inspection possible. Plus, OSS flows should work on it. Use one beam fab for cheap ones plus one for at least 90nm with 65nm or 45nm high-end.
Far as recent companies, the eASIC process is maskless at 90nm, 45nm, and 28nm for prototyping. THey mainly do structured ASIC's. Here's an example of the prototyping cost:
By "not FIB lithography" I meant he isn't using the FIB machine to make shadow masks for photolithography; he's directly using them on the semiconductor, like Alacron. I'm not sure of the brand of his machine.
You'd think FIB milling (and deposition and implantation) should be able to do considerably better than the 28 nanometers you can do with photolithography these days (after investing a billion dollars in your fab, anyway). The de Broglie wavelength of a heavy ion isn't that big.
The eASIC link you give implies, without saying, that eASIC ASICs aren't "cell-based ASICs", but that's what "structured ASICs" are, and WP at least confirms that the Nextreme ASICs described in that link in particular are cell-based.
It's not totally clear to me that eASIC is in fact using FIBs for their prototypes; is that based on you talking to people at the company?
I agree that the per-unit cost for FIB is enormous. I hadn't thought about the possibility of using many beams at once to reduce that cost.
Re do better. I've skimmed enough papers on the stuff to say the physics is too complex for me to have an opinion either way. It's the implementation issues they're always fighting, though.
Re masks. I know. The reason I mention it is they're both essentually drawn by hand a piece at a time. Showing why one is too slow to use for significant volumes should enlighten you on other. Yet, if tiny volumes, might be acceptable but machines cost $$$.
Re eASIC. eASIC uses a multiple, eBeam machine for theirs. They might have more than one. They directly write the stuff onto the naterial. That it's a S-ASIC defined by one, custom layer is why it's so quick and cheap. A full ASIC has many layers so price/time goes way up.
Btw, I'd be interested in an email from the guy to ask him a few questions. Im especially interested if he needs a cleanroom, how he packages them, and what software is like to assess subversion counters at interface level.
I do part time work packaging FIBbed gizmos, the 'machinist' has done at best a 50nm diameter aperture in metal film (from what I recall, maybe it was 100nm) using a beam diameter of 10nm. This is on a machine that was new 20 years ago (newer machines are probably 5 to 10X better in terms of hardware these days, maybe 50X in software). Also, ASML is researching multi-beam electron steppers and getting more traction lately: http://semiengineering.com/multi-beam-market-heats-up/ (from 2 months ago)
So, what's involved in packaging them? I'm thinking along the lines of me coming up with a custom circuit that I print onto silicon, package into a chip, and put that sucker on a PCB. I figured the packaging would take similarly, specialized equipment given it's so tiny. Is it built into FIB equipment? Extra? How easy is it to use?
I always see articles on the ebeams and FIB showing how they work. Nothing on packaging.
Oh, by 'package' I meant heat-seal in plastic bags. 'Packaging' a silicon chip for electrical use should be pretty similar regardless of the production technique, given chemical compatibility, stress/strain of the chip and how packaging would add/affect that. There's wirebonding which is basically soldering wires from the silicon to some larger package-scale traces/larger-wires (often embedded in the package structure). There are a few ways of getting the actual FIBbed gizmo onto something macro-scale. Sometimes the thing you start with is large enough to handle easily, sometimes you bring in a CNC manipulator, use FIB to solder your gizmo to the manipulator, move the manipulator elsewhere and then 'tack weld' down your gizmo there and mill away the connection to the manipulator. Some systems have micro/nano vacuum manipulators. I bet on the high-end piezos are used to move things, but I am sure at some relatively larger scale mechanical movement wouldn't be too hard to use (depending on how cheap you need things to be, and how many times you want to repeat doing such connections).
